New Cadence Virtuoso Platform Delivers Fast, Silicon-Accurate Custom Design

Virtuoso Raises the Bar with Integrated Multi-mode Simulation, greater than 10x Faster Accelerated Layout, Advanced Silicon Analysis Available on OpenAccess Database

The Virtuoso platform is available on both the industry-standard OpenAccess database and the popular Cadence CDBA database. With the Virtuoso platform, design teams can quickly design silicon that is right and on time at process geometries from 1 micron down to 90 nanometers and beyond.

With this platform, Cadence is upgrading all of its existing custom technologies and shipping several new products. The new Virtuoso Multi-mode Simulation provides SPICE, FastSPICE, AMS, and RF capabilities - all utilizing common syntax, models, and equations. Virtuoso LE Turbo adds design-rule driven, QuickCell parameterized cell specification, and wire-to-wire editing capabilities to Virtuoso LE. The platform also adds Virtuoso AMS Silicon Analysis for 130 nanometers and smaller circuits, and Virtuoso HF-AMS silicon analysis, which includes additional capabilities for greater than 1GHz circuits.

"Predictability and productivity are critical for today's advanced custom designs," said Lavi Lev, Cadence executive vice president and general manager. "They require the speed of top-down design combined with the silicon accuracy of bottom-up design - all in a comprehensive environment. That's something only the Virtuoso platform delivers."

Custom digital, analog, RF, and mixed-signal design becomes exponentially more complex and faces exponentially more physical effects as companies move to more aggressive process technologies. These demands have become extremely acute as companies integrate high-performance custom circuitry with massive digital designs at 130 nanometers and beyond. Until now, the electronic design industry's core custom design tools and environments have not kept pace. The Virtuoso platform significantly raises the bar, providing extensible, new-generation capabilities which enable a fast, silicon-accurate design methodology. Importantly, the platform preserves existing investments in current Cadence custom technologies and environments as design teams migrate to the OpenAccess database.

"The Cadence Virtuoso custom design platform will be the backbone of our next-generation mixed-signal flow," said Jean Pierre Geronimi, CAD Director of Central R&D Design Automation at STMicroelectronics. "Our decision was mainly driven by the productivity gain we have seen both in the point tools and the new OpenAccess database infrastructure. More specifically: for tools, we have much appreciated the enhancements to Virtuoso, CCAR power routing and Preview, particularly in the area of 130- and 90-nanometer support, where we contributed with our process specifications, while, in the OpenAccess space, we were very pleased with the capacity and performance seen in the new OA-native Virtuoso Chip Editor for managing the final Chip Finishing phase of the Physical Design."

Multi-mode Simulation

With the Virtuoso platform, Cadence is the only company to offer SPICE, FastSPICE, AMS, and RF simulation as both best-of-breed standalone simulators and in a single multi-mode simulation licensing model - Virtuoso Multi-mode Simulation - which allows users to select the simulation type at runtime. All Virtuoso simulators utilize common syntax, models, and equations ensuring identical results at the highest accuracy settings. Moreover, these are the same models and equations generated by the Virtuoso advanced device modeling tools. This powerful combination supports fast full-chip top-down simulation, silicon-accurate bottom-up simulation, and everything in between. Other enhancements include 3x faster SPICE performance and full HSPICE compatibility.

"A fast, silicon-accurate design platform is critical to successful mixed-signal and RF designs, especially on advanced process technologies," said Ed Chen, Director of Services Product Marketing at TSMC. "Today, the Virtuoso platform supports TSMC's 90 nanometer process requirements and models. Our broad alliance with Cadence is differentiated by a joint focus on silicon-accuracy ranging from the characterization and simulation of the latest generation of models through the co-development of TSMC process design kits (PDKs) that support the Virtuoso platform."

Accelerated Layout

In the Virtuoso platform, Cadence has boosted performance in its accelerated layout tools by over 10x, cutting complex operations from minutes to seconds and making most operations nearly instantaneous. Design-rule driven support ensures correct-by-construction layout, which is especially important 130 nanometers and below. Additional enhancements include OpenAccess support for up to 3x capacity and rectilinear floorplanning within Virtuoso XL. The recently announced Virtuoso Chip Editor provides fast, full-chip integration for custom, cell-based, and mixed-implementation designs.

"National has been very successful using the Virtuoso accelerated layout in our analog and mixed-signal designs," said Bill Meier, senior CAD manager at National Semiconductor's Technology Infrastructure Group. "Its connectivity-driven capability is key to fast correct-by-construction layout, and the platform's ability to easily run parasitic re-simulation in the Virtuoso platform is a real plus."

Silicon Analysis

For analog/mixed-signal design at 0.18 microns and below, high-accuracy parasitic extraction, analog IR-drop analysis, and power-grid electromigration analysis become critical for circuit design and full-chip electrical verification. The new Virtuoso AMS Silicon Analysis product combines all of these capabilities with design rule checking (DRC) and layout-versus-schematic checking (LVS). The new Virtuoso HF-AMS Silicon Analysis adds inductance extraction, electromigration, and a field solver for high-frequency (greater than 1GHz) analog/mixed-signal designs. These capabilities enable design teams to quickly perform silicon-accurate analysis that can save extremely expensive unplanned-respins.

OpenAccess Support

Virtuoso full-chip integration takes advantage of the industry-standard OpenAccess database to eliminate the massive file transfers otherwise needed for SoC chip finishing and ECO flows. OpenAccess also enables seamless, bidirectional data exchange between the Cadence Virtuoso and Cadence Encounter(TM) platforms for improved productivity.

Advanced Custom Design Methodology

With the release of the Virtuoso platform, Cadence is also publishing the Virtuoso Advanced Custom Design (ACD) Methodology, which will be posted to the Cadence Web site by mid-October. Based on industry best practices, ACD outlines a practical "meet-in-the-middle" approach that combines the speed of top-down design with the silicon-accuracy of bottom-up design. Cadence plans to evolve this methodology and use it to guide Virtuoso platform development.

In addition, the company is delivering the Virtuoso Analog/Mixed-Signal Baseline Flow based on the ACD methodology. This detailed, step-by-step flow is based on a distributable reference design and PDK. It is immediately available via demonstrations, hands-on workshops, documentation, training, and methodology services. Cadence plans to deliver additional baseline flows over the next year.

Pricing and Availability

The Cadence Virtuoso custom design platform is available immediately on HP, Sun, IBM, and Linux platforms. Specific operating-system support varies by product. U.S. pricing for a one-year license starts at $140,000 for Virtuoso Multi-mode Simulation, $15,000 for Virtuoso Accelerated Layout, $100,000 for Virtuoso Silicon Analysis. The platform also includes enhanced versions of all existing custom tools.

About Cadence

Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,000 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence, Virtuoso and the Cadence logo are registered trademarks, and Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Agilent Technologies and AMI also endorse the Cadence Virtuoso custom design platform:

AGILENT TECHNOLOGIES: "Agilent remains committed to the RF Alliance with Cadence and to delivering industry-leading RF/mixed-signal IC design technology through the Virtuoso custom design platform," Jim McGillivary, vice president, EEsof EDA Division, Agilent Technologies. "We look forward to delighting our mutual customers with a unified design infrastructure that brings RFIC designers into the mainstream custom IC design flow."

AMI: "As a long-time Cadence customer, we expect multi-mode simulation to help us meet our customers' stringent time-to-market requirements more easily," said Dwayne Sherrard, CAD group director at AMI Semiconductor. "The combination of common simulation models for silicon accuracy and a flexible master simulation license within a customizable framework is very attractive. We've had great success with Cadence custom technology, and we expect the Virtuoso platform will help us leverage that investment into providing next-generation designs for our customers."

CONTACT: Cadence Design Systems, Inc.
             Judy Erkanat, 408-894-2302
             jerkanat@cadence.com